The present invention relates generally to integrated circuit (IC) designs, and more particularly to a design for a system-on-chip (SoC) including a core logic circuit, a memory module and an analog circuit with switched capacitors.
In an IC industry, an SoC is typically comprised of a digital logic circuit, a memory module, and an analog circuit. The logic circuit includes core transistors and I/O or peripheral transistors. The core transistors can be a plurality of high-speed transistors having thin gate dielectrics. The I/O transistors can be a plurality of low-speed transistors having thick gate dielectrics. The memory module, such as a DRAM cell array, is comprised of a number of memory cells, each of which typically includes an access transistor and a storage capacitor, such as a metal-insulator-metal (MiM) capacitor. The equivalent silicon oxide thickness (EOT) of gate dielectric of the access transistor is designed to be thicker than that of the core logic transistor in order to prevent leakage current that hampers the functionality of the DRAM cell. The storage capacitor holds a bit of information—0 or 1. When the storage capacitor is charged with electrons, it represents logic 1. When the storage capacitor is empty, it represents logic 0. The access transistor allows a control circuitry to read or write the capacitor. Due to the current leakage of the capacitor, the control circuitry needs to recharge or refresh all the capacitors holding logic 1s by reading the cells and then writing logic is right back into them. This refresh operation happens automatically thousands of times in one second. When the DRAM cells are off power, their data disappears. The analog circuit often includes a switched capacitor circuit comprised of two switched capacitors, two switched transistors, and an operational amplifier. In order for the switched capacitor circuit to function properly, the ratio of capacitance between the two switched capacitors needs to be kept at a very precise level.
Conventionally, although the transistors of the analog switched capacitor circuit are fabricated substantially during the same processes as those for making the transistors in the digital logic circuit, the capacitors of the switched capacitor circuit are fabricated in a process separate from those by which the storage capacitors of memory cells are fabricated. This increases manufacturing costs and reduces yield rates, which become increasingly significant in higher generations of semiconductor processing technology, such as the 90 nm generation.
Moreover, the conventional fabrication process for the switched capacitor circuit constructs the switched capacitors in a planar fashion, instead of a vertical fashion. As a result, the conventional switched capacitor tends to be bulky, and usually occupies a large area.
Thus, it is desirable to design a method and system for implementing an SoC including a logic circuit, a memory module and an analog circuit that utilizes layout area efficiently, and can be fabricated cost-effectively.